The MIPI-DSI standard, which is a serial interface standard standardized by the MIPI alliance for communications between a processor and a peripheral device (e.g. a display device) in a portable device, has a feature of high-speed communication with low power consumption.
In data communications in accordance with the MIPI-DSI standard, one clock lane and one to four data lanes are used. Each lane includes two signal lines (a pair of signal lines) which transmit a differential signal. In detail, the clock lane includes two signal lines (a pair of signal lines) which transmits a differential clock signal and each data lane includes two signal lines which transmits a differential data signal.
The MIPI-DSI standard prescribes two communication modes: the LP (low power) mode and the HS (high speed) mode. The LP mode is a communication mode for performing communications at low speed but with low power consumption, and the HS mode is a communication mode for achieving high-speed communications. Transitions between the LP and HS modes in each of the clock lane and the data lanes are achieved by switching the voltage levels on the two signal lines of each of the clock lane and the data lanes in predetermined sequences by the transmitting side. The receiving-side circuit recognizes a transition of the communication mode on the basis of the voltage levels on the two signal lines of each of the clock lane and the data lanes.
A receiving-side circuit may incorrectly determine that the data communication is switched from the HS mode to the LP mode, when noise is applied to the clock lane while a data communication is performed in the HS mode. This may cause an undesired halt of the data communication in the HS mode. It would be desirable to suppress such an undesired influence of noise.
It should be noted that communications in accordance with the MIPI-DSI standard in a liquid crystal display device is disclosed in, for example, Japanese Patent Application Publication No. 2012-150152 A.